1. Field of the Invention
This invention relates to structures and methods of assembly of integrated circuit chips into interconnected multiple chip modules. More particularly, this invention relates to multiple chip structures connected physically and electrically.
2. Description of the Related Art
The manufacture of embedded Dynamic Random Access Memory (DRAM) requires that process parameters that enhance the performance of the logic or the DRAM, if separately formed on semiconductor chips, be compromised when DRAM is embedded into an array of logic gates on the same semiconductor chip. This compromise has limited the application of embedded DRAM. If there is no compromise in the process parameters to enhance the performance of logic or the embedded DRAM, the manufacturing process becomes very complicated and costly. Moreover, because of the structure of the embedded DRAM and the logic, burn-in of the embedded DRAM is not possible and embedding of DRAM with logic is not a reliable design solution.
A multiple chip module structure is a viable alternative to embedded DRAM. With multiple chips connected in intimate contact, the process parameters that maximize the performance of the DRAM chip and the logic gates can be applied during manufacture. Refer to FIG. 1 for a description of a “chip-on-chip” structure 100. Such a “chip-on-chip” structure is described in U.S. Pat. No. 5,534,465 (Frye et al.). A first integrated circuit chip 105 is attached physically and electrically to a second integrated circuit chip 110 by means of an area array of solder bumps 115. The process of forming an area array of solder bumps 115 is well known in the art and is discussed in Frye et al. 465. The second chip 110 is then secured physically to a substrate 120. Electrical connections 125 between the second integrated circuit chip 110 and external circuitry (not shown) are created as either wire bonds or tape automated bonds. The module further has a ball grid array 130 to secure the structure to a next level of packaging containing the external circuitry. Generally, an encasing material 135 is placed over the “chip-on-chip” structure 100 to provide environmental protection for the “chip-on-chip” 100.
U.S. Pat. No. 5,481,205 (Frye et al.) teaches a structure for making temporary connections to integrated circuit chips having “solder bumps” or connection structures such as ball grid arrays. The temporary connections allow temporary contacting of the integrated circuit chip during testing of the integrated circuit chip.
The handling of wafers from which the integrated circuit chips are formed and the handling of the integrated circuit chips themselves causes the integrated circuit chips to be subjected to electrostatic discharge (ESD) voltages. Even though connections between the first integrated circuit chip 105 and the second integrated circuit chip 110 are relatively short and under normal operation would not be subjected to ESD voltages, ESD protection circuitry is required to be formed within the interchip interface circuit to provide protection or necessary driving capacity for the first integrated circuit chip 105 and the second integrated circuit chip 110 during burn-in and other manufacturing monitoring processes.
U.S. Pat. No. 5,731,945 and U.S. Pat. No. 5,807,791 (Bertin et al.) teach a method for fabricating programmable ESD protection circuits for multichip semiconductor structures. The interchip interface circuit on each integrated circuit chip is formed with an ESD protection circuit and a switch to selectively connect the ESD protection circuit to an input/output pad. This allows multiple identical chips to be interconnected and redundant ESD protection removed.
The circuits at the periphery of integrated circuit chips generally are specialized to meet the requirements of standardized specifications. These include relatively high current and voltage drivers and receivers for communicating on relatively long transmission line media. Alternately, as shown in U.S. Pat. No. 5,461,333 (Condon et al.) the interface may be differential to allow lower voltages on the transmission line media. This requires two input/output pads for transfer of signals.
U.S. Pat. No. 5,818,748 (Bertin et al.) illustrates a separation of chip function onto separate integrated circuits chips. This allows the optimization of the circuits. In this case, EEPROM is on one integrated circuits chip and drivers and decoders are on another. The chips are placed face to face and secured with force responsive self-interlocking micro-connectors.
FIGS. 2a and 2b show multiple “chip-on-chip” structures 100 constructed on a wafer. Not shown is the forming of the first integrated circuit chip on a silicon wafer. The first integrated circuit chip is tested on the wafer and nonfunctioning chips are identified. The wafer is separated into the individual chips. The functioning first integrated circuit chips 105 then are “flip-chip” mounted on the second integrated circuit chip 110 on the wafer 200. The wafer 200 is then separated into the “chip-on-chip” structures 100. The “chip-on-chip” structures 100 are then mounted on the modules as above described.